sam.hadow/Random-access-machine
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Sam Hadow 2024-03-25 09:13:05 +01:00
parent b36389841f
commit a0096369c2
1 changed files with 57 additions and 13 deletions
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70
src/ram.py
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@ -7,44 +7,88 @@ class Ram(object):
self.output_registers = [] # O registers
self.work_registers = [] # R registers
def read_register(self, type, index, ref_origin=None, ref_target=None):
def read_register(self, type_register, index, ref_origin=None, ref_target=None):
'''
Read from a register
'''
if type == "input":
self.current += 1
if type_register == "input":
return self.input_registers[index]
elif type == "work":
elif type_register == "work":
value = self.work_registers[index]
if value is None:
raise ValueError("register empty")
else:
return self.work_registers[index]
elif type == "output":
elif type_register == "output":
raise TypeError("output registers are write only")
elif type == "value":
elif type_register == "value":
return index
elif type == "reference":
elif type_register == "reference":
target_index = self.read_register(ref_origin, index)
return self.read_register(ref_target, target_index)
def write_register(self, type, index, value, ref_origin=None, ref_target=None):
def write_register(self, value, type_register, index, ref_origin=None, ref_target=None):
'''
Write to a register
'''
if type == "input":
self.current += 1
if type_register == "input":
raise TypeError("output registers are read only")
elif type == "work":
elif type_register == "work":
if len(self.work_registers) <= index:
self.work_registers.extend([None] * (index + 1 - len(self.work_registers))) # extend with uninitialized values
self.work_registers[index] = value
elif type == "output":
elif type_register == "output":
if len(self.output_registers) <= index:
self.output_registers.extend([None] * (index + 1 - len(self.output_registers))) # extend with uninitialized values
self.output_registers[index] = value
elif type == "value":
elif type_register == "value":
raise TypeError("cannot write on value")
elif type == "reference":
elif type_register == "reference":
target_index = self.read_register(ref_origin, index)
self.write_register(ref_target, target_index, value)
def op(self, type_op, r1, r2, r3):
if type_op == 'add':
value_1 = self.read_register(r1)
value_2 = self.read_register(r2)
value_3 = value_1 + value_2
self.write_register(value_3, r3)
elif type_op == 'sub':
value_1 = self.read_register(r1)
value_2 = self.read_register(r2)
value_3 = value_1 - value_2
self.write_register(value_3, r3)
elif type_op == 'div':
value_1 = self.read_register(r1)
value_2 = self.read_register(r2)
value_3 = value_1 / value_2
self.write_register(value_3, r3)
elif type_op == 'mul':
value_1 = self.read_register(r1)
value_2 = self.read_register(r2)
value_3 = value_1 * value_2
self.write_register(value_3, r3)
def op_ctrl(self, type_op, z, r1=None, r2=None)
if type_op == 'jump':
if isinstance(z, int):
self.current += z
else:
raise ValueError("wrong operand type (should be integer)")
if type_op == 'je':
value_1 = self.read_register(r1)
value_2 = self.read_register(r2)
if value_1 == value_2:
self.op_ctrl('jump', z)
else:
self.current += 1
if type_op == 'jl':
value_1 = self.read_register(r1)
value_2 = self.read_register(r2)
if value_1 > value_2:
self.op_ctrl('jump', z)
else:
self.current += 1