refactor, move set_bits to new file
This commit is contained in:
+3
-43
@@ -1,6 +1,7 @@
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from tea3.pretty_print import pretty_print
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from tea3.pretty_print import pretty_print
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from tea3.cliutils import prompt_int, prompt_choice, prompt_list
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from tea3.cliutils import prompt_int, prompt_choice, prompt_list
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from tea3.tea3model import Tea3Model
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from tea3.tea3model import Tea3Model
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from tea3.utils import set_bits
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from tea3.variable_search import run_exhaustive, run_exhaustive_staircase, run_exhaustive_staircase2, run_exhaustive_bp
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from tea3.variable_search import run_exhaustive, run_exhaustive_staircase, run_exhaustive_staircase2, run_exhaustive_bp
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from tea3.sbox import run_sbox
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from tea3.sbox import run_sbox
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from tea3.variable_xor import run_variable_xor, run_exhaustive_xor
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from tea3.variable_xor import run_variable_xor, run_exhaustive_xor
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@@ -38,47 +39,6 @@ def run_classic_cli():
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print("\n" + "=" * 50)
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print("\n" + "=" * 50)
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print("Done.")
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print("Done.")
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def _set_bits(model, bit_names, value):
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if value not in (0, 1):
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raise ValueError("value must be 0 or 1")
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const = model.S.one() if value else model.S.zero()
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for raw in bit_names:
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name = raw.strip()
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if not name:
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continue
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if len(name) != 3 or not name[1:].isdigit():
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raise ValueError(
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f"Invalid bit name '{name}'. Expected formats like R00, x00, r10."
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)
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prefix = name[0]
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reg = int(name[1])
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bit = int(name[2])
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if prefix == "R":
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if not (0 <= reg <= 7 and 0 <= bit <= 7):
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raise ValueError(f"Invalid R bit '{name}'. Use R00..R77.")
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model.R_bits[reg][bit] = const
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elif prefix == "x":
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if not (0 <= reg <= 4 and 0 <= bit <= 7):
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raise ValueError(f"Invalid x bit '{name}'. Use x00..x47.")
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model.x_bits[reg][bit] = const
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elif prefix == "r":
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if not (0 <= reg <= 4 and 0 <= bit <= 7):
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raise ValueError(f"Invalid r bit '{name}'. Use r00..r47.")
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model.r_bits[reg][bit] = const
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else:
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raise ValueError(
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f"Invalid bit name '{name}'. Expected R, x, or r."
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)
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def run_advanced_cli():
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def run_advanced_cli():
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print("\nR registers are indexed 0–7; bits within each register are 0–7.")
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print("\nR registers are indexed 0–7; bits within each register are 0–7.")
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print("x and r registers are indexed 0–4; bits within each register are 0–7.")
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print("x and r registers are indexed 0–4; bits within each register are 0–7.")
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@@ -99,8 +59,8 @@ def run_advanced_cli():
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try:
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try:
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# 1 overrides 0
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# 1 overrides 0
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_set_bits(model, zero_bits, 0)
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set_bits(model, zero_bits, 0)
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_set_bits(model, one_bits, 1)
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set_bits(model, one_bits, 1)
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except ValueError as e:
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except ValueError as e:
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print(f"Error: {e}")
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print(f"Error: {e}")
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return
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return
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@@ -0,0 +1,48 @@
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from sage.all import GF, BooleanPolynomialRing
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from functools import reduce
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from operator import mul
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def set_bits(model, bit_names, value):
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"""
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Set the given bits to a constant value (0 or 1) in the model.
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bit_names: list of strings like 'R00', 'x12', 'r47'.
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value: 0 or 1.
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"""
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if value not in (0, 1):
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raise ValueError("value must be 0 or 1")
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const = model.S.one() if value else model.S.zero()
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for raw in bit_names:
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name = raw.strip()
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if not name:
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continue
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if len(name) != 3 or not name[1:].isdigit():
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raise ValueError(
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f"Invalid bit name '{name}'. Expected formats like R00, x00, r10."
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)
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prefix = name[0]
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reg = int(name[1])
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bit = int(name[2])
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if prefix == "R":
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if not (0 <= reg <= 7 and 0 <= bit <= 7):
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raise ValueError(f"Invalid R bit '{name}'. Use R00..R77.")
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model.R_bits[reg][bit] = const
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elif prefix == "x":
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if not (0 <= reg <= 4 and 0 <= bit <= 7):
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raise ValueError(f"Invalid x bit '{name}'. Use x00..x47.")
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model.x_bits[reg][bit] = const
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elif prefix == "r":
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if not (0 <= reg <= 4 and 0 <= bit <= 7):
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raise ValueError(f"Invalid r bit '{name}'. Use r00..r47.")
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model.r_bits[reg][bit] = const
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else:
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raise ValueError(
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f"Invalid bit name '{name}'. Expected R, x, or r."
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)
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