fix in assembly file

2024-04-09 18:27:06 +02:00
parent cd1d6382fd
commit fa92ee4364
2 changed files with 4 additions and 3 deletions
--- a/src/ram.py
+++ b/src/ram.py
@@ -103,9 +103,10 @@ class Ram(object):
        Run machine to completion
        '''
        while self.current < len(self.instr):
-            print(self.current)
-            print(*self.instr[self.current]['args'])
+            print(self.current+2)
+            #print(*self.instr[self.current]['args'])
            self.instr[self.current]['op'](self, *self.instr[self.current]['args'])
+            print(self.work_registers)

    def generate_graph(self):
        '''