sam.hadow/Random-access-machine
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flex + bison

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Sam Hadow
2024-03-25 13:37:10 +01:00
parent 2a3907eef7
commit 4ba1dbb9d4
3 changed files with 129 additions and 22 deletions
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44
src/ram.py
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@@ -11,20 +11,19 @@ class Ram(object):
'''
Read from a register
'''
self.current += 1
if type_register == "input":
if type_register == "i": # input
return self.input_registers[index]
elif type_register == "work":
elif type_register == "r": # work
value = self.work_registers[index]
if value is None:
raise ValueError("register empty")
else:
return self.work_registers[index]
elif type_register == "output":
elif type_register == "o": # output
raise TypeError("output registers are write only")
elif type_register == "value":
return index
elif type_register == "reference":
elif type_register == "@": # reference
target_index = self.read_register(ref_origin, index)
return self.read_register(ref_target, target_index)
@@ -32,63 +31,63 @@ class Ram(object):
'''
Write to a register
'''
self.current += 1
if type_register == "input":
raise TypeError("output registers are read only")
elif type_register == "work":
if type_register == "i": # input
raise TypeError("input registers are read only")
elif type_register == "r": # work
if len(self.work_registers) <= index:
self.work_registers.extend([None] * (index + 1 - len(self.work_registers))) # extend with uninitialized values
self.work_registers[index] = value
elif type_register == "output":
elif type_register == "o": #output
if len(self.output_registers) <= index:
self.output_registers.extend([None] * (index + 1 - len(self.output_registers))) # extend with uninitialized values
self.output_registers[index] = value
elif type_register == "value":
raise TypeError("cannot write on value")
elif type_register == "reference":
elif type_register == "@": # reference
target_index = self.read_register(ref_origin, index)
self.write_register(ref_target, target_index, value)
def op(self, type_op, r1, r2, r3):
if type_op == 'add':
self.current += 1
if type_op == 'ADD':
value_1 = self.read_register(*r1)
value_2 = self.read_register(*r2)
value_3 = value_1 + value_2
self.write_register(value_3, *r3)
elif type_op == 'sub':
elif type_op == 'SUB':
value_1 = self.read_register(*r1)
value_2 = self.read_register(*r2)
value_3 = value_1 - value_2
self.write_register(value_3, *r3)
elif type_op == 'div':
elif type_op == 'DIV':
value_1 = self.read_register(*r1)
value_2 = self.read_register(*r2)
value_3 = value_1 / value_2
self.write_register(value_3, *r3)
elif type_op == 'mul':
elif type_op == 'MULT':
value_1 = self.read_register(*r1)
value_2 = self.read_register(*r2)
value_3 = value_1 * value_2
self.write_register(value_3, *r3)
def op_ctrl(self, type_op, z, r1=None, r2=None):
if type_op == 'jump':
if type_op == 'JUMP':
if isinstance(z, int):
self.current += z
else:
raise ValueError("wrong operand type (should be integer)")
if type_op == 'je':
if type_op == 'JE':
value_1 = self.read_register(*r1)
value_2 = self.read_register(*r2)
if value_1 == value_2:
self.op_ctrl('jump', z)
self.op_ctrl('JUMP', z)
else:
self.current += 1
if type_op == 'jl':
if type_op == 'JL':
value_1 = self.read_register(*r1)
value_2 = self.read_register(*r2)
if value_1 > value_2:
self.op_ctrl('jump', z)
self.op_ctrl('JUMP', z)
else:
self.current += 1
@@ -101,10 +100,11 @@ class Ram(object):
### example
input_registers = [10, 5]
input_registers = [10, 5, 1]
instructions = [
{'op': Ram.op, 'args': ('add', ('input', 0), ('value', 1), ('output', 2))},
{'op': Ram.op, 'args': ('ADD', ('i', 0), ('value', 1), ('o', 2))},
{'op': Ram.op, 'args': ('ADD', ('value', 0), ('@', 2, 'i', 'i'), ('o', 1))},
]
ram = Ram(instructions, input_registers)